Semiconductor memory devices include dynamic random access memories (DRAMs). Recently, the mainstream use of DRAMs has shifted toward synchronous DRAMs (SDRAMs). A virtual channel SDRAM (VCSDRAM) has been proposed in Japanese Patent Application No. Hei 9-290233. VCSDRAMs can be desirable as they can further increase an access speed for a SDRAM.
A virtual channel memory, such as a VCSDRAM, can include a memory cell array having a number of memory cells, such as DRAM memory cells arranged in a row direction and a column direction. In addition, a virtual channel memory can also include a register array having registers arranged into a predetermined number of rows and a predetermined number of columns. The register array rows and columns can correspond to the rows and columns in the memory cell array. The register array can take the form of a static random access memory (SRAM) and have a cache function.
One particular type of system that can utilize DRAMs is a parallel processing system. A parallel processing system can include a number of central processing units (CPUs) and a number of controllers that are connected to bus lines. The bus lines are connected to a register array that is combined with a memory cell array. The register array can operate as a cache memory. In the parallel processing arrangement, one cache memory can be used by a plurality of CPUs and a plurality of controllers. Such an arrangement can lead to a more simplified system structure.
One particular application for a VCSDRAM is that of a graphic memory. A graphic memory can store image data. In many graphic memory operations, the same data (e.g., "0" or "1") is frequently written into or read from a large number of memory cells at the same time. One example of such an operation is when image data is reset. Accordingly, when a VCSDRAM is used as a graphic memory, the same data is frequently stored in the memory cell array and the register array. In a conventional approach, when the same data is to be written into a memory cell array and the register array, the write data will be written from external input/output pins to the memory cell array and the register array one by one. For example, if a register array includes registers arranged in an m.times.n array, data can be written into m.times.n memory cells. The same data must then be written into m.times.n registers of the register array. As a result, image reset operations can consume a considerable amount of time.
In light of the above, it would be desirable to provide a memory device that may be used with image processing that can reduce the period of time required for reading or writing data when an image is reset. It would also be desirable that such a memory device be a VCSDRAM.